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System Peripherals and Debug Access Port
Figure 12: HPS with Dual-Core ARM Cortex-A9 MPCore Processor
AV-51001
2013.12.26
Configuration
Controller
Lightweight
FPGA-to-HPS HPS-to-FPGA HPS-to-FPGA
FPGA Fabric
FPGA-to-HPS SDRAM
Debug
Access Port
ETR
FPGA
Manager
HPS
MPU Subsystem
ARM Cortex-A9 MPCore
(Trace)
CPU0
CPU1
SD/MMC
Controller
Ethernet
MAC (2x)
ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management Unit
ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management Unit
Multiport
DDR SDRAM
Controller
with
Optional ECC
USB
OTG (2x)
Level 3
Interconnect
ACP
SCU
NAND Flash
Controller
DMA
Controller
STM
Level 2 Cache (512 KB)
64 KB
Boot ROM
64 KB
On-Chip RAM
Peripherals
(UART, Timer, I 2 C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and
Quad SPI Flash Controller)
System Peripherals and Debug Access Port
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated
DMA controller. For modules without an integrated DMA controller, an additional DMA controller module
provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are
multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes and supports ARM
CoreSight debug and core traces to facilitate software development.
Altera Corporation
Arria V Device Overview
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